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Nexperia 74LVC(H)16373A-Q100 D-Type Transparent Latches

Nexperia 74LVC(H)16373A-Q100 D-Type Transparent Latches feature separate D-type inputs with bus hold (74LVCH16373A-Q100 only) for each latch and 3-state outputs for bus-oriented applications. One Latch Enable (LE) input and one Output Enable (OE) are provided for each octal. The inputs can be driven from either 3.3V or 5V devices, but when disabled, up to 5.5V can be applied to the outputs. These features allow the use of these devices in mixed 3.3V and 5V applications.

The Nexperia 74LVC(H)16373A-Q100 16-bit D-type transparent latches incorporate CMOS technology with low power consumption and multibyte flow-through standard pinout architecture. These devices consist of two sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition, the latches are transparent; the latch outputs change each time its corresponding D-input changes.

These products are qualified for the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and are suitable for automotive applications.

Features

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
  • Specified from -40°C to 85°C and from -40°C to 125°C temperature range
  • 5V tolerant inputs/outputs for interfacing with 5V logic
  • Wide supply voltage range from 1.2V to 3.6V
  • CMOS low power consumption
  • Multibyte flow-through standard pinout architecture
  • Multiple low inductance supply pins for minimum noise and ground bounce
  • Direct interface with TTL levels
  • All data inputs have bus hold (74LVCH16373A-Q100 only)
  • High-impedance when VCC=0V
  • Complies with JEDEC standard
    • JESD8-7A (1.65V to 1.95V)
    • JESD8-5A (2.3V to 2.7V)
    • JESD8-C/JESD36 (2.7V to 3.6V)
  • ESD protection
    • MIL-STD-883, method 3015 exceeds 2000V
    • HBM JESD22-A114F exceeds 2000V
    • MM JESD22-A115-A exceeds 200V (C=200pF, R=0Ω)
    • CDM ANSI/ESDA/Jedec JS-002 exceeds 1000V

Functional Diagram

Block Diagram - Nexperia 74LVC(H)16373A-Q100 D-Type Transparent Latches
View Results ( 4 ) Page
Numéro de pièce Fiche technique Nombre de circuits Type de logique Famille logique Nombre de lignes de sortie Courant de sortie de haut niveau Courant de sortie de bas niveau Délai de propagation Tension d’alimentation - Min. Tension d’alimentation - Max. Nombre de canaux Nombre de lignes d'entrée Courant d’alimentation maximal Élément par puce Package/Boîte
74LVC16373ADGV-Q1J 74LVC16373ADGV-Q1J Fiche technique 2 Circuit CMOS, TTL LVC 16 Line - 24 mA 24 mA 6 ns 1.2 V 3.6 V 2 Channel 16 Input 80 uA TVSOP-48
74LVCH16373ADGV-QJ 74LVCH16373ADGV-QJ Fiche technique 2 Circuit CMOS, TTL LVCH 16 Line - 24 mA 24 mA 6 ns 1.2 V 3.6 V 2 Channel 16 Input 80 uA 2 Element TVSOP-48
74LVC16373ADGG-Q1J 74LVC16373ADGG-Q1J Fiche technique LVC TSSOP-48
74LVCH16373ADGG-QJ 74LVCH16373ADGG-QJ Fiche technique 2 Circuit CMOS, TTL LVCH 16 Line - 24 mA 24 mA 6 ns 1.2 V 3.6 V 2 Channel 16 Input 80 uA 2 Element TSSOP-48
Publié le: 2019-05-29 | Mis à jour le: 2023-04-27