AMD / Xilinx LogiCORE™ IP JESD204C Core Software
AMD LogiCORE™ IP JESD204C Core Software implements a JESD204C-compatible interface supporting line rates from 1Gbps to 32.5Gbps (the maximum line rate depends on the transceiver type and speed grade of the selected device). The user can configure the JESD204C core to transmit or receive using either a 64B66B or 8B10B link layer. The AMD LogiCORE™ IP JESD204C Core Software is fully backward compatible with JESD204B.
Features
- Designed to JEDEC® JESD204C.1 Standard
- Supports GTY, GTYP, and GTM (NRZ only) transceivers on AMD Versal™ adaptive SoCs
- Supports GTH and GTY transceivers on AMD UltraScale+™ and AMD UltraScale™ devices
- Supports up to eight lanes per core and a greater number of lanes using multiple cores
- Supports 64B66B and 8B10B link layers
- Supports FEC Encoding (TX) and Decoding (RX) on the 64B66B link layer
- Supports CRC-12, CMD, and FEC metadata modes on the 64B66B link layer
- Supports subclasses 0 and 1 on the 64B66B link layer and subclasses 0, 1, and 2 on the 8B10B link layer
- Provides physical and data link layer functions when used with the Versal adaptive SoC Transceiver Wizard for Versal adaptive SoCs and JESD204_PHY core for UltraScale and UltraScale+ devices (Note: The Versal adaptive SoC Transceiver Wizard is used directly by the JESD204C core, and the JESD204_PHY is no longer required)
- AXI4-Lite configuration interface
- AXI4-Stream data and command interfaces
- Supports transceiver sharing between TX and RX cores using the JESD204_PHY core or Versal adaptive SoC Transceiver Wizard
Publié le: 2026-06-23
| Mis à jour le: 2026-06-23
